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APFC (Active Power Factor Correction Rectifier) is just one kind of AC-DC converter, which achieve low current harmonic distortions and high power factor.
buck converter
One possibility is the gate drive signal coupled to the power stage. This happens to the high side Ntype boost strap gate drive when you has damping resistor connected in between high side gate and source.
It looks like a forward converter without reset wiring. Please check your schematic. For your question, the voltage loop may need compensation; at mean while, your current loop may or may not need a compensation slope for current loop stability. Look up the current mode control material or text...
I guess input impedance makes it happen. With voltage divider, your input cap (Cin) has a pole at 1/2/pi/1.25MOhm/Cin. However, you without voltage devider, you put a zero output impedence voltage source there, which means there is no pole for this case.
Function work and cost are always the main considerations. Basic digital control chip (PID type) in nowadays takes more chip area than analog comtroller. Besides, adc and digital Digital PWM resolution and delay are the other constrains for digital design. However, digital control can do some...
I think it is nest miller compensation, but the small signal you draw is not exactly the same as your circuit.
There is another forward signal path from gain stage 1 to output node. There is a good reference for you. Please read "Analysis and Design of Analog IC" by Gray and Meyer, Fig. 9.33...
Hi, all,
I think the analysis is correct.
However, there is a forward gain from Vin to V(-) node.
which is -R2/(R1+R2).
By adding this term all equations are correct.
Vo=-A*V(-)
V(-)=R2/(R1+R2)*Vin+R1/(R1+R2)*Vo
Here R1/(R1+R2) is beta
R2/(R1+R2) is forward gain
Loop gain T is still...
Hi, all
I am interested in the low voltage reference voltage generation, such as below 0.5V.
Does anyone knows a way to do that? Any reference material is appreciate.
Hi, all,
I am trying to model the core loss in spice simulation. Does anyone know how to do that? or any reference document will be appreciate. Thank you.
dc-dc converter matlab
For average model, there are some lib and example from "Fundamental of Power Electronics" by Maksimovic
**broken link removed**
For state space model, you can take L and C as states derive the state sapce in simulink, that works as well.
Things can be teken into two parts: (switching effect and charges in the channel)
1. At beginning, Vd=Vs=0, then Vg starts to decrease. Befoer Vg hit the Vth, channel is still there, which means the drain and source are connected by a on resistance (on resistance values changes). since Vg...
Hi, all
I am designing a latched comparator (dynamic type).
How can I set up the simulation to get the performance in offset and speed??
I also need Monte Carlo and Corner model verification. Thank you.
leg1234
I have a question about power mofset model.
In the datasheet, Cgs does not change much with different Vds. However, Vds changes, the operation model will change as well, which means the gate-channel capacitance will goes to drain or source by different operation mode (triode or saturation). Can...
There are some chips which work for control and gate drive for battery charger. Those chips have build in level shifter and bootstrap circuit for high side floating drive.
Using SEPIC, you need low side drive only, however, SEPIC cannot give you continuous current output.
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