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Thanks for telling me your findings, I don't know if my codes passed Synplify Pro a good or bad thing. It helps implement my design faster but it also hides some of my language specification problems at the same time. Lol.
Hi, it does read and write, and I guess it is the synthesis behavior. I don't try it on Quartus, but my design didn't pass the Lattice LSE. Thank you for your reply.
Thank you for your reply, Dave.
My board has been working fine with the assign sentence. I don't really need this wire a here, I wonder the assign is not strictly from RHS to LHS in this 'inout 'case. If it is, the 'inout' should be working as an 'input' only.
I did map D to port_a, my...
Hello,
I have a verilog design and I don't know why it works...
////Top_level////
module tricky_design(port_a,......);
inout [5:0] port_a; //in & out, physically connects to GPIOs of DSP on my board for read and write.
wire [5:0] a;
assign a = port_a; // Question here...
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