Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by LAORUAN

  1. L

    should the function and task which represent hardware be automatic or static?

    Thanks for your reply. So, the sentence below is not right? Because a task or function represents the behavior of a single piece of hardware can also be automatic? • If a task or function represents the behavior of a single piece of hardware, and therefore is not re-entrant, then it should be...
  2. L

    should the function and task which represent hardware be automatic or static?

    I think that, when the function is implemented into hardware in multiple locations, the function is called for multiple times at the same time. So, the function should be re-entrant. Do I misunderstand it? Do you mean the function or task representing hardware should be automatic? The...
  3. L

    should the function and task which represent hardware be automatic or static?

    •If a task or function is to be re-entrant, it should be automatic.The variables also ought to be automatic, unless there is a specific reason for keeping the value from one call to the next. As a simple example, a variable that keeps a count of the number of times an automatic task or function...
  4. L

    what's the difference between "Manual Override" and "Manual Clock Switchover" in C4

    what's the difference between "Manual Override" and "Manual Clock Switchover" in C4 what's the difference between "Manual Override" and "Manual Clock Switchover" in Cyclone IV? I know that "Manual Override" is used in Automatic Clock Switchover mode. However, as far as I am concerned, the only...
  5. L

    The question about Opposite-Edge Capture Center-Aligned Input in Altera AN433

    I practice the Opposite-Edge Capture Center-Aligned DDR input in Quartus II. I only contrait the false path, and then, I get the right result.
  6. L

    The question about Opposite-Edge Capture Center-Aligned Input in Altera AN433

    This image comes from Altera AN433. As we can see, AN433 requires to constraint the Opposite-Edge Capture Center-Aligned Input with multicycle and false path exception. However, in my opinion, we just have to constraint that with false path exception which would remove the analysis of same-edge...
  7. L

    Question about the constrait of output clock in source-synchronous outputs interface

    hello, every one. My question is as follow: #************************************************************** # Create Clock #************************************************************** create_clock -name {iCLK} -period 20.000 -waveform { 0.000 10.000 } [get_ports {iCLK}] create_clock -name...
  8. L

    how to use -source_latency_included option in set_input_delay?

    Thank you. Gernerally, I use the set_clock_latency to set the latency of the clock of FPGA. Do you mean that I have to set the latency of the clock of external device?
  9. L

    how to use -source_latency_included option in set_input_delay?

    Thank you for your reply. I have read the on the "set_input_delay" on "Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Timing Analysis" book. But I still have a doubt on that. As we can see, the input delay includes the source latency without source_latency_included.
  10. L

    how to use -source_latency_included option in set_input_delay?

    what does these sentence mean? Input delays can already include clock source latency. By default the clock source latency of the related clock is added to the input delay value,but when the -source_latency_included option is specified, the clock source latency is not added because it was...

Part and Inventory Search

Back
Top