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It depends on if rst signal is synchronized or not. At the time rst is released (DFF become not reset) you do not hope clock toggle the flip flop at that time because it may induce race. So generally you should add constraint between clock and rst. Or rst can be synchronized before sent to clock...
Re: how to understand def format, cadence
LEF contains the information of "pin", such as metal layer and location. DEF just represent the connection of pins on those LEFs. So extaction with DEF and LEF can get the connection informaion of all "black box" (LEF). This connection information is...
Re: ESD - diodes
If the pdiode is made with p+/nwell and the ndiode is made with n+/psub there are indeed two reasons for choosing pdiode.
1. If n+/psub is used it need salicide block layer (SBLK or SAB) to add ballasting resistance. Otherwise current filamentation will happen under ESD. But...
Re: Damaging IO input
It depends on the relationship of this IO pin with that VCC/GND. If VCC/GND is the power/ground this IO uses then it will be no problem. Otherwise issue of damage may happen.
Re: the power down mode
The fundmental idea of power down is to attain zero power consumption. So in digital domain we use a power down signal to make logic element stay in logic high or low ( current is zero at this time). In analog domain tie PMOS bias or NMOS bias node to power or ground can...
Re: bandgap
First build a standard 1.2v output BGR then generate current through a resistor. Mirror this current through another resistor then you will get 1.5v BGR. Remember to match these two resistors.
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