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Recent content by kurukuru

  1. K

    Request for Mico32 porting to spartan3E dev board resources

    Hi, I was playing around with mico32 using lattice board and now want to port it to spartan3E dev board which I've heard that it can be done. But problem is, I don't have much idea about how to deal with this and there is no available resource (ex. breif, tutorial or design step). So it...
  2. K

    newbie's VHDL code, comment please

    Hi, Thank you very much Ilgaz and xtcx for your answer. I have checked PAR of the code shown below according to the advice. The result is there is no different in both number of gate used and maximum frequency. !!! Ps. I’m still opening for more comments and advices Thank you. kurukuru...
  3. K

    newbie's VHDL code, comment please

    Hi, I write VHDL code by separating main state and output control from each others. Main process contains only change of state and in output process I monitor main state and change output value accordingly. For me it is very easy to design and read but I don't know whether it is a poor...
  4. K

    Please, would like to have verilog wrapper example code

    Thank you very much again for your kindly reply. I will try this as soon as I can.
  5. K

    Please, would like to have verilog wrapper example code

    Hi, Thank you very much Shitansh for your kindly reply. Would it bother if I ask more things? I would like to know where in Verilog code that I can place my to be wrapped VHDL code, before or after mapping Verilog pinout to VHDL pinout or wherever? And what if I have generic in my VHDL...
  6. K

    Please, would like to have verilog wrapper example code

    Hello, I’m trying on using LatticeMico32 as a main CPU aiming to create a CPU that surround by my own peripheral IP module. The problem is when import custom IP module to a system, CPU platform builder (Lattice MSB) supports only Verilog and I know only VHDL. However the manual suggests that...
  7. K

    Please guide me to match this timing diagram

    Thank you very much again shitansh, I finally matched this timing diagram and get sound out from my codec IC already. By the way, It's still a lot of noise. I think may be because by un-continue CODEC data input cause by my code which I'm going to fix.
  8. K

    Please guide me to match this timing diagram

    Thank you very much shitansh, Did you mean put both BCK and LRCLK in the sensitivity case of process and then something like detect rising edge of LRCLK then start shift my digital data with BCK? But I know mean to detect rising edge only use lach and double latch then comparing both to find...
  9. K

    Please guide me to match this timing diagram

    Thank you very much FvM for you answer. Sorry for my stupidly mistake on BCK. But may you explain more that LRCK is frame synchronization. For my understand, I have to shift all off my L-Channel audio during '1' of LRCK and R-Channel during '0' of LRCK. But what I would like to ask is when...
  10. K

    Please guide me to match this timing diagram

    The attachment is timing diagram of DAC codec IC PCM3008 (16 bit serial) that I would like to interface using FPGA. As in the diagram I have already create LRCK (which is sampling freq. 32kHz) and BCK (which is bit shifting freq. 512kHz) by divide my clock input. The problem is I don't know...
  11. K

    Is this kind of code is one-hot coding style

    one hot coding Thank you very much shastri.vs. I got it now
  12. K

    Is this kind of code is one-hot coding style

    one hot fsm and grey code fsm Thank you very much shastri.vs for your reply. So you mean that my code is ready to be One-hot encoding. what I have to do is just select encoding style option in my synthesis program. Am I wrong? By the way, I use Lattice FPGA and ispLever as a synthesis...
  13. K

    Is this kind of code is one-hot coding style

    code style one hot Hi all, I am a newbie in FPGA using VHDL language, I was told by my friend to try to write my code using state machine coz it easy to read and debug. I have coded my circuit as shown below and I’m wondering that whether this coding style called one-hot or not? (FYI, I have...
  14. K

    Need explanation of FSM, information on VHDL systems design

    Re: FSM I was confused about it too. I reccomend Circuit Design with VHDL book by Volnei A. Pedroni chapter 8.
  15. K

    How to choose Critical Path

    Hi, vlsi_whiz, Thank you very much for your kindly reply.
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