Please guide me to match this timing diagram

[kurukuru]

The attachment is timing diagram of DAC codec IC PCM3008 (16 bit serial) that I would like to interface using FPGA.
As in the diagram I have already create LRCK (which is sampling freq. 32kHz) and BCK (which is bit shifting freq. 512kHz) by divide my clock input.
The problem is I don't know how to detect when to start shif my data from first bit to last bit respectively since LRCK and BCK is freely run from the start.
Would anyone guide me by provide me some guide? VHDL code also appreciate as well as others suggests.

Thank you

 

[FvM]

I have already create LRCK (which is sampling freq. 32kHz) and BCK (which is bit shifting freq. 512kHz)

Not correct. Even in your unclear diagram (there are much better in any TI PCM chip datasheet), you see, that BCK must be at least 32*fs respectively 1024 kHz.

I don't know how to detect when to start shift my data.

LRCK is the frame synchronisation.

 

[kurukuru]

Thank you very much FvM for you answer.

Sorry for my stupidly mistake on BCK. But may you explain more that LRCK is frame synchronization.

For my understand, I have to shift all off my L-Channel audio during '1' of LRCK and R-Channel during '0' of LRCK.
But what I would like to ask is when my digital data is ready to be sent, which I don't know when on this time diagram,
are there better way to create timing diagram than use latch to detect rising egge of LRCK then count variable parameter and shift Din to meet BCK timing.

Thank you in advance.

 

[shitansh]

Hi,

Say your shifting clock is BitClk and slower clock is FrameClk. So for your case BitClk = FrameClk x 32.

So when posedge of FrameClk detected in BitClk domain you need to start shiting your data which is 32 bit wide. You will achive this staisfactorly as your FrameClk = BitClk/32.

So on next rising edge of FrameClk your data will be available at out put.

Same way on reciver side you have to do.

--
Shitansh Vaghela

 

[kurukuru]

Thank you very much shitansh,

Did you mean put both BCK and LRCLK in the sensitivity case of process and then something like

detect rising edge of LRCLK then start shift my digital data with BCK?

But I know mean to detect rising edge only use lach and double latch then comparing both to find rising edge.

Do you think this is the best way to detect rising edge or if there are others way pls tell me.

 

[shitansh]

Did you mean put both BCK and LRCLK in the sensitivity case of process and then something like

I am not getting what you understand please be more clear

detect rising edge of LRCLK then start shift my digital data with BCK?

Yes exactly this you have to do.

But I know mean to detect rising edge only use lach and double latch then comparing both to find rising edge.

Do you think this is the best way to detect rising edge or if there are others way pls tell me.

Yes this is one way you can do this another way to detect rising edge of FrameClk in BitClk domain is FSM. But use only synchronized output in that.



I hope this link may help you for this. This is simulation result of attached verilog file.
https://obrazki.elektroda.pl/50_1252300669.jpg


--
Shitansh Vaghela

 

[kurukuru]

Thank you very much again shitansh,

I finally matched this timing diagram and get sound out from my codec IC already.

By the way, It's still a lot of noise. I think may be because by un-continue CODEC data input cause by my code which I'm going to fix.