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Recent content by kumarans

  1. K

    Reg the Advance node metal routing

    Dear All, May I know the reason why we are not using the 45 degree metal routing in 14nm and below tech nodes. Kindly clarify. Rgds KumaranS
  2. K

    Standard Verification Rule Format (SVRF) Manual

    Hai This is KUmaran, Looking for the SVRF guide, I am not able to loacte the pdf in the specific path . help me Rgds Kumaran.S
  3. K

    Is the common centroid method obsolete ?

    Re: Common centroid Hai Guys, I have one dout which below mentioed pattern is good and avoid the gradient and offset voltage?????????? ABAB ABBA BABA vs. BAAB ABAB BAAB BABA ABBA Rgds Kumaran.S Added after 10 minutes: Hai Guys , Here I have attached the basic PDF...
  4. K

    common centroid diff pair layout

    Hai Guys, I have one dout which below mentioed pattern is good and avoid the gradient and offset voltage?????????? ABAB ABBA BABA VS BAAB ABAB BAAB BABA ABBA Rgds Kumaran.S
  5. K

    which common centriod pattern is better 4 differential pair?

    Hai Guys, I have one dout which below mentioed pattern is good and avoid the gradient and offset voltage?????????? ABAB ABBA BABA vs. BAAB ABAB BAAB BABA ABBA Rgds Kumaran.S
  6. K

    Common Centroid & Interdigitization

    Hai Guys, I have one dout which below mentioed pattern is good and avoid the gradient and offset voltage?????????? ABAB ABBA BABA vs. BAAB ABAB BAAB BABA ABBA Rgds Kumaran.S
  7. K

    Newgui To LAYOUT - can u share skill files, how to start

    Re: Newgui To LAYOUT Hai guys ,this the forum you can have all discussions reg the analog layout & design nd for SKILL Check this session: Rgds Kumaran.s
  8. K

    Looking for IC Backend Engineer

    physical design engineer resume Hai I am interested in this job and looking forward to work in SG, I am around 4yrs exp and working in IC LAYOUT DESIGn and circuit Design. In brief 7 months I worked in NUS then 3.2yrs in STM as a contractor in CIO [CMOS IO] team,now in KPIT as a client i am...
  9. K

    Reg the placement of IO in ring

    can u able to send me the site or where I can download. because I have trying for reg but i cant so kindly help me
  10. K

    suggestion for I/O pads AMS 0.35um

    Can any one have the documents related to this topic it whould be helpfull to get a clear IDEA
  11. K

    Comparison between hierarchical check and flatten check

    flatten hierarchy calibre when a same cell is placed more than once the H-cell is best to clear LVS.Calibre do it best.
  12. K

    Reg the placement of IO in ring

    i/o reg Hai, In Io ring placement , how will we calculate the power pad placement in between IO placement,is any one having Document related to IO ring placement. what kind of resistance calculation involved in it. try to clear my douts. Thx Kumaran.S
  13. K

    High-to-low level shifter

    1.8v to 3.3v level shifter U can use the balance level shifter or traditional one like inverter out is given to the cascaded nmos and pmos as a input and the output is given to the inverter.
  14. K

    the problem of well isolation

    Floating substrate create huge Noise
  15. K

    Looking for papers about CMOS Matching

    CMOS Matching for good reference refer AT OF ANALOG LAYOUT book its gives u a good idea of MATCHING
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