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Recent content by KTy

  1. K

    Using PIC USB physical layer for slave-slave communication

    Re: Using PIC USB physical layer for slave-slave communicati You seem not to have understood my question/reasonning... :cry:
  2. K

    Using PIC USB physical layer for slave-slave communication

    usb physical layer Hi guys, (whoa, 7 posts in 5 years :D ) Here is my project, I am digging for feasability... I would like to build a device that could be connected to a PC as a "normal USB slave device"; for this I was thinking using 18F2550. With the amount of documentation on the net...
  3. K

    M@delsim 5.5e problem: Fatal: Bad pointer access

    Actually I solved my pb easily... There were 'space' in my project path... M@delSim didn't like that... It works fine now.
  4. K

    M@delsim 5.5e problem: Fatal: Bad pointer access

    I have also the same problem with M@delSim 5.7d (# ** Fatal: (SIGSEGV) Bad pointer access.) My guess it's that it is related to winXP... Any solution ???
  5. K

    Looking for ISL6215 datasheet (Intersil)

    I*S*L*6*2*1*5 datasheet Anyone has this ? It's from Int*er*sil. This is for I*n*t*e*l I*M*V*P core regulation. Thanks !
  6. K

    Int*l sp**dSt*p documentation...

    ...replace '*' with 'e'... Does anyone have this ? Best, KTy
  7. K

    Which synthesis tool to use with a FPGA ?

    Ok, right, i have "only" about 70k gates... I have actually pb with clock skew... So i'll need to try "Amplify" ? Is that from Synplicity too ? Btw, i found that there are way less options in Synplify rather than in Leonardo Spectrum. I have Symplify 7.0.2, shoud i try the 6.2 version ? Thx a...
  8. K

    Which synthesis tool to use with a FPGA ?

    I'm currently using Synplify from Synplicity and LeonardoSpectrum from Mentor but i can't make my design work properly at every try because of the timing constraint and the bad optimiser. My target is a FLEX10k130e FPGA running at 60MHz. Any advice would be helpfull... KTy

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