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Recent content by Kriz Adrivan

  1. K

    Biasing two stage amplifier

    Hi Siddhartha, My professor recently gave us a two-stage opamp schematic with PMOS input pair to design. Most books and videos deal with NMOS input pair. However, for a PMOS input pair, I'm a bit confused on how to get the equations for the Vin(max) and Vin(min). I tried solving for Vin(max)...
  2. K

    [SOLVED] Synopsys LVS Error: What does this error mean?

    Hi Sathishkrishna, Thanks for the reply. Anyway, I solved it already. In case you're wondering, the error was the portlist was not defined for the poly resistor that I was using. I solved it by modifying my NetTran Options under the Netlisting Option tab to point to my "empty.subckt" file.
  3. K

    [SOLVED] Synopsys LVS Error: What does this error mean?

    Hi all, I'm doing a layout on a two-stage amplifier. However, when I run LVS, there is an error and LVS Debbuger window won't show up as it normally would. I cannot seem to fix it. Does anybody know what this error means? **broken link removed**

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