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in power dissipation i think the second one will dissipate more compared to the first one because it always connected to vdd so there must be always a minimam level of power dissipation even when the input is zero.
here are the links for the above mentioned magazines
EFY – India's first magazine on Electronics news, Products, Components, Industry: electronicsforu.com
Elektor India
Nuts and Volts
http://www.electronicsmaker.com
---------- Post added at 17:54 ---------- Previous post was at 17:52...
the second circuit that you have given might work it depend on the timing of the components.what i mean is that the flipflop input required to be present for some delay before the clock arrive inorder to work correctly.here the clock is fed from the xor.the only time delay between the input and...
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