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in this fig minimum connections required for latch up are shown.. The arrow (white colored) near p+ to n+ is the electron path. If .7 volts drop in that region below source, it will trigger latch up.. Hence what i wanna ask, is there any other possibility where this NPNP structure will form...
why does latch up occur only in CMOS technology? Is there any possibilities of Latch up in other than CMOS technology..? i.e. in NMOS, PMOS alone.. or cobination of those..
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