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Recent content by koti

  1. K

    Job opportunity / partnership

    Hi Can you please send me your personal email id my email id cherukuri.koti@gmail.com Thanks Koti
  2. K

    How to increase LEFAbstract Generator Resolution(Cadence)

    Hello All, Can you please explain how to increase LEF Resolution using Abstract Generator tool(v5.5). When i was export the LEF, resolution is 2 digits but layout contains 3 digits. Most unmatch are caused by resolution. Ex: RECT 9.11 295.02 3.11 300.00 but in layout RECT 9.115 295.025...
  3. K

    New PCB Design and Manufacturing company(India)

    top manufacturing companies india Hello All, I am planning to start new company in PCB design and manufacturing domain. I have 5 years experience in RF design and analog design. Can you please share your ideas and experience? I will be search for partner of my new company. Thanks & Regards Koti
  4. K

    Help, Calibre LVS Error report (DPR19)

    default calibre case option Hello Benbenbear, I can't find any attachment in this post. Can you please upload error file and environment variables setup. I will try my level best to fix this issue. Thanks Koti
  5. K

    Standard Verification Rule Format (SVRF) Manual

    svrf_ur.pdf Hello ald356, Please find the below link **broken link removed** This is calibre 2004.4 version. Thanks & Regards Koti
  6. K

    hi, can u give me GD micro systems web site link

    gd microsystems Hello Ravitest, GD micro wed site. **broken link removed** Qualcore logic website. **broken link removed** Thanks & Regards Koti
  7. K

    Before start to do VCO layout

    Hi Ninge, 1) Devices formation & fabbrication process. 2) Design rule document and GDS layer usage. 3) Basic knowledge on design capture & verification tools (cadences, laker. mentor, etc) 4) Follow the guidelines (matching, current ratings, critical nets, routing, etc) 5) Specifications...
  8. K

    Using a Schottky diode on Virtuoso Schematic

    schottky diode schematic Hi, Generally any diode used in a schematic it should be specify area,pj(junction parameter),model. layout designer calculate length and width according to the area & pj(if length & width also specify in schematic their is no problem). Thanks & Regards Koti. Added...
  9. K

    Checklist for creating a schematic diagram

    guidelines in making a schematic diagram Hi Ramesh, this are the guidelines for creating proper schematics 1) maintain visibility 2)proper functionality 3)reduce complexity 4)good looking and easily understandable. 5)indicate current ratings, matching requirements and sensitive nodes 6)use...
  10. K

    IC Station and Virtuoso, which leads the other?

    user friendly, point to point net router, we can generate layout directly from schematic
  11. K

    How to draw a schematic with 8 transistors in parallel in Orcad Capture?

    Re: question on capture Hi, I am using different tools for schematic capture like cadence and viewlogic so it is not 100% correct answer but i will tray to suggest my best effots(Below options use it). 1)In transistor attributes(properties) define multiplier property(MULT) and assign value or...
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