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Hi guys,
I’ll start working with a new PDK on a CMOS node I’m not familiar with. What simulations would you recommend for analog & mixed-signal high speed IC design purposes to get familiar with device models?
I’m thinking some basic inverter sim and dc sweeps to establish Vt, ft and parasitic...
Hi,
I'm designing a wireless transmitter that consists of a DAC, a switched-cap baseband filter and a passive upconverter. I'm trying to simulate the spectral performance (ACLR and EVM) and produce constellation plots using QAM signals. The signals have been generated in MATLAB with RRC pulse...
Hi,
I've been experimenting with envelope analysis in Cadence and would like to plot the constellation and EVM for a QAM 16 modulated signal. I used the rectangular 16QAM block from rfLib in my testbench.
In SpecteRF wireless envelope analysis, there is the option of printing the constellation...
Hi guys,
First of all, I apologize in advance if my question makes no sense, but this is the first time I am dealing with an entire RF transmitter. For my research project in grad school I designed an RF transmitter that includes a digital baseband (SPI and SRAM for loading the IQ samples)...
I noticed that the new MMSIM environment by Cadence provides specific sources for LTE, WiLAN, ZigBee and other wireless standards. These sources can be simulated along with the wprobe using the "wireless" option in the envelope analysis to plot directly EVM, constellations, and spectrum (with...
Thank you, pancho_hideboo! So, if I understand correctly, you're suggesting I generate a SystemVerilog component using the HDL Verifier in Simulink and then using this as a behavioral model in AMS-Designer. Would this, however, solve the issue of sharp transitions in my high-speed square-wave...
Thank you very much, BigBoss. I have access to ADS, but I'm not sure how I can make it work with Simulink. Does ADS support PWL sources like SpectreRF, where I can load the baseband CDMA samples?
I am trying to simulate my transmitter (TX) design in SpectreRF (Cadence). I have created a schematic with ideal components (from analogLib) and Verilog-A models for the digital gates. I want to simulate the complete TX using a real cellular signal, such as CDMA or LTE. For this purpose, I have...
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