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Characterizing new CMOS tech

KostasRF

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Hi guys,

I’ll start working with a new PDK on a CMOS node I’m not familiar with. What simulations would you recommend for analog & mixed-signal high speed IC design purposes to get familiar with device models?

I’m thinking some basic inverter sim and dc sweeps to establish Vt, ft and parasitic caps such as Cgs/W, for starters
 

dick_freebird

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I would add to the list, some model vs data review especially regarding params that MOS models aren't so great at covering - leakage / GIDL / DIBL, gate and drain kink / curl, etc. - realizing this data may not willingly be shared and it's presentation in PDK docs is meant to sell the "ready for prime time" story that the modeling engineers want, not show you the "warts". I have seen modeling reports where the IVs step right over mid-Vds*mid-Vgs OP region where SOI drain kink "lives" - after debugging a comparator that turned out to be ruined by this phenomenon with no hint in the sims.
 

BigBoss

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Start with DC swept simulations to learn the characteristics of the PDK.
Use different W/L ratio-for instance- and check out the IV curves.
 

NARENDRA1234

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i would do dc sweeps with different W and L ration and different bias currents and VGS. DO this with diode connected mosfets. this way you will know what the VGS is for requireed current or vice versa..
also i would do gm curve and W/L and VGS.

that helps too.
 

stober

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i would do dc sweeps with different W and L ration and different bias currents and VGS. DO this with diode connected mosfets. this way you will know what the VGS is for requireed current or vice versa..
also i would do gm curve and W/L and VGS.

that helps too.
I always do a lookup table from this. Extracting most of the parameters I'm interested, gm, gds, gm/gds, gm/id, noise, flicker noise corner and index (interestingly it's not always 1), Cgs, Cgd, ft, mismatch, etc. I call them my rulers.
 

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