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Recent content by kollosse

  1. K

    triggerd 16bit Counter - how can i reset a set register?

    trigger'd 16bit Counter Hi, how can i reset a set register? The counter starts at the rising edge of clk1, then the counter counts up to FFFFh and stops. module counter Title '16bit counter' Declarations clk pin 5; clk1 pin 6; count_en node istype 'reg'; d0 pin 24 istype...
  2. K

    ABEL XST VHDL (ISE 4.2) COUNTER

    ece446 iit Hi, i have the following problem (ABEL XST VHDL) ISE 4.2. Declarations clk pin 5; d0 pin 27 istype 'reg'; d1 pin 26 istype 'reg'; d2 pin 25 istype 'reg'; d3 pin 24 istype 'reg'; count=[d3,d2,d1,d0]; Equations count.CLK = clk; :?: :?: :?: // How can i...
  3. K

    16 bit Upcounter in VHDL (ISE 4.2 )

    Hi, how can i progammed a 16bit upcounter under VHDL. I use ISE 4.2 and a XC9572XL PLCC44 CPLD (XILINX) How must i assing the Counter-outputs [D15..D0] to the pins. Sorry but my english is not so good. Johann
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