ABEL XST VHDL (ISE 4.2) COUNTER

[kollosse]

ece446 iit

Hi,

i have the following problem (ABEL XST VHDL) ISE 4.2.


Declarations

clk pin 5;
d0 pin 27 istype 'reg';
d1 pin 26 istype 'reg';
d2 pin 25 istype 'reg';
d3 pin 24 istype 'reg';

count=[d3,d2,d1,d0];
Equations
count.CLK = clk;
:?: :?: :?:
// How can i d this??
WHEN (clk rising edge) then
count = count+1;

thanks

Johann

 

[maestor]

I think you just use:

count := count+1;

it uses the rising edge of the count.CLK (if you want to use the falling edge I guess you need to invert the CLK before asigning it to count.CLK)

there is an example in this App:

**broken link removed**

page 4

I hope it helps.

- maestor