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pin lvs
I'm trying to finish the project and I have the problem, after planing the IO cells like GND & VDD for core logic (GND3IP & VDD3IP) and power supply output buffers (GND3OP & VDD3OP). Running Assura LVS (with Macro LVS) and have two short first between 'gnd!' and 'A' second 'vdd3o!' and...
Hi,
I'm do inverter in ASIC and have problems, can't create pins in layout.
When I imports pin from schematic to layout, DRC and LVS don't see this pins.
Are two warning
1. Floatinf Poly1
2. Floating gate not connect to s/d, pad or resistor.
J'm use Assura for DRC and LVS, and Hit Kit AMS...
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