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Probelm with pin in assura LVS

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kleppo

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pin lvs

I'm trying to finish the project and I have the problem, after planing the IO cells like GND & VDD for core logic (GND3IP & VDD3IP) and power supply output buffers (GND3OP & VDD3OP). Running Assura LVS (with Macro LVS) and have two short first between 'gnd!' and 'A' second 'vdd3o!' and 'A' . What I am doing wrong. I work Cadence IC6.1.3.1 and AMS Hit of 4.0.
 

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