Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by kky1024

  1. K

    [SOLVED] IBM 130 chipedge and chip guard ring

    Thanks for replying! I find a tutorial for IBM process. It is useful!
  2. K

    [SOLVED] IBM 130 chipedge and chip guard ring

    Hi friends, I am using IBM 130nm process to tape out a full-custom design, using Cadence Virtuoso 6.1.5. But how can I create the chipedge? I just use the "chipedge" layer, but there are sooooo many DRC problems:-o. I am new to tape out. Can any one help me? Thanks so much! Best, Tony

Part and Inventory Search

Back
Top