[SOLVED] IBM 130 chipedge and chip guard ring

[kky1024]

Hi friends,

I am using IBM 130nm process to tape out a full-custom design, using Cadence Virtuoso 6.1.5. But how can I create the chipedge? I just use the "chipedge" layer, but there are sooooo many DRC problems:-o. I am new to tape out. Can any one help me? Thanks so much!

Best,
Tony

 

[dick_freebird]

Do you need to do that? Some foundries insist to do it in
their CAD group, not trusting the dumb customer.

See if any of the libraries (like the one with the pads in it)
has a "scribe" or "die seal" PCell? No way would any foundry
want you to free-hand it, there's a standard they want to
see and either they provide you a good cell that you can't
mess up, or they mean to do it after tape-in (just like the
density fills and other fab specific, non-circuit features).

 

[kky1024]

Do you need to do that? Some foundries insist to do it in
their CAD group, not trusting the dumb customer.

See if any of the libraries (like the one with the pads in it)
has a "scribe" or "die seal" PCell? No way would any foundry
want you to free-hand it, there's a standard they want to
see and either they provide you a good cell that you can't
mess up, or they mean to do it after tape-in (just like the
density fills and other fab specific, non-circuit features).

Thanks for replying! I find a tutorial for IBM process. It is useful!

 

[Cuauhtemoc]

Thanks for replying! I find a tutorial for IBM process. It is useful!

Hello kky1024,

I have the same problem with the chip edge and chip guard ring. Could you share the "useful IBM process tutorial".

Any body have another reference?

Thank you!