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Hi,
I'm designing mixed signal circuits.
digital circuits are synthesized by Design Compiler and P&R is performed by using Astro.
In the floorplan stage, i made core area, power/ground ring, horizontal power/ground rail for standard cells.
But, after making floorplan, input/output singal...
Thanks all for your comment.
The problem was that the reset was released at clock rising edge.
I made the reset to be released at falling edge of the clock, and then problems are solved.
Hi,
I am training ASIC synthesis and P&R using Design compiler and Astro with a simple 5-bit synchronous counter RTL code.
I use synopsys VCS as a simulator.
I synthesized RTL code and generated gate-level verilog netlist.
In the gate level simulation with gate-level verilog netlist and...
Hi, everyone.
referencing the i2c slave RTL code supported by opencores.org, internal clock frequency is 48MHz.
I don't fully understand internal operation of I2C slave. but higher frequency internal clock than external data rate seems to be needed.
internal clock samples SCA and SDA.
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