[SOLVED] Hold time violation(?) in VCS

[kks0716]

Hi,

I am training ASIC synthesis and P&R using Design compiler and Astro with a simple 5-bit synchronous counter RTL code.

I use synopsys VCS as a simulator.

I synthesized RTL code and generated gate-level verilog netlist.

In the gate level simulation with gate-level verilog netlist and standard cell verilog model library provided by process vendor using VCS, following errors were occurred.

I did not know the reason why these errors occurred.

In the synthesis phase, i used "set_fix_hold [get_ports clk]" and set 1ns hold margin so that no hold/setup violation occurred. clock period was 10ns

but in the gate-level simulation phase, these errors occurred. i don't know the meaning of these errors.

please anyone help me.


Command: ./simv -l simv.log
Chronologic VCS simulator copyright 1991-2011
Contains Synopsys proprietary information.
Compiler version E-2011.03; Runtime version E-2011.03; May 14 11:24 2012
Warning! From $vcdplusfile at time 0 in file ../rtl/counter5b_tb.v line 19: [VCD+-OOSA]:
Only one string argument is allowed.
Task ignored.
VCD+ Writer E-2011.03 Copyright (c) 1991-2011 by Synopsys Inc.



"../lib/u300lscsp33gdr_sdf21.v", 5579: Timing violation in counter5b_tb.u_counter5b.out_reg_4_
$hold( posedge CK:120000, posedge RB:120000, limit: 1000 );

"../lib/u300lscsp33gdr_sdf21.v", 5579: Timing violation in counter5b_tb.u_counter5b.out_reg_3_
$hold( posedge CK:120000, posedge RB:120000, limit: 1000 );

"../lib/u300lscsp33gdr_sdf21.v", 5579: Timing violation in counter5b_tb.u_counter5b.out_reg_2_
$hold( posedge CK:120000, posedge RB:120000, limit: 1000 );

"../lib/u300lscsp33gdr_sdf21.v", 5579: Timing violation in counter5b_tb.u_counter5b.out_reg_1_
$hold( posedge CK:120000, posedge RB:120000, limit: 1000 );

"../lib/u300lscsp33gdr_sdf21.v", 5579: Timing violation in counter5b_tb.u_counter5b.out_reg_0_
$hold( posedge CK:120000, posedge RB:120000, limit: 1000 );

Finished all tests
$stop at time 280000 Scope: counter5b_tb File: ../rtl/counter5b_tb.v Line: 30

exit
V C S S i m u l a t i o n R e p o r t
Time: 280000 ps
CPU Time: 0.940 seconds; Data structure size: 0.1Mb
Mon May 14 11:24:43 2012

 

[yx.yang]

When you do gate sim, you may need back annotate the *.sdf at simulation. The *.sdf can be generate from DC/PT, at last it generate from the P&R tool.

 

[sakthikumaran87]

This errors signifies that the clk changes at the same time as your RB while a hold of 1000 has been defined as minimum hold requirement. Check whether the path is a false path. If so declare it as a false path. Else you have to probe for the reason of failure to meet the timing.

 

[kks0716]

Thanks all for your comment.

The problem was that the reset was released at clock rising edge.

I made the reset to be released at falling edge of the clock, and then problems are solved.

 

[vikadik]

I think it comes down to your timescale you use for your gate level sims.