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Hi guys,
The op-amp I am working on is used to sense changes in very small capacitance(femtofarads). To get a predefined sensitivity, the input capacitance of the op-amp is limited to 1pF. I tried the usual topologies like two-stage miller op-amp, folded cascode, telescopic cascode etc. For all...
In brief:
When a process is being characterized, MOSFETs of different W/L's are fabricated and various voltages and currents applied and their responses measured using high precision equipment. The captured data is then used to build compact models (BSIM3 for MOSFETs etc) using tools like...
Did you try applying a current limited power supply(Something like a bench-top RPS) to your Vref and check if the reference input is internally damaged.
You have to do a simple thing called MOSFET characterization. You basically vary VDS and VGS to get a set of I-V curves. From those you can extract all the process parameters needed for your hand calculations.
The data you see in those .scs files is for BSIM3v3. You see, MOSFETs are...
They are the corners of that process, They are used to see if the circuit will still be in spec when NMOS transistors are "slower" than PMOS and vice-versa.
For NMOS,PMOS
tt - Typical, Typical
ff - Fast, Fast
ss - Slow, Slow
sf - Slow, Fast
fs - Fast, Slow
If your circuit simulation results...
I am not sure of the synthesis tools but for optimization, there is a company called MunEDA that specializes in such areas.
PS: I've never used their software
Thank You for all the replies. The problem has been rectified.
The method suggested by erikl did the job, with one small change. I couldn't get DC analysis to take prevoppoint ( I understand that it is mainly used for small-signal (AC, stb etc) analysis? ). What I did was to use the writefinal...
I can do that but I have one small problem(I think). I am using one of those capacitor startup circuits that turns itself off when the circuit is biased properly. The only way (I know of) to trigger that startup circuit is with a varying(ramp, however short it may be) voltage on the supply line...
Thank You, I tried it but that didn't work in this case. The error amp is (self)-biased from the bandgap, unless DC-Analysis can wait till the currents have properly settled the simulation output is going to be wrong. Any advice?
The following is for a Bandgap circuit simulation.
How can I set spectre to do DC analysis only after the VDD (vpwl) is completely ramped up. The transient simuation shows proper response but the DC analysis is being performed at t=0 which happened to be Vdd=0.
I tried setting the order in...
I am making a radio modem using one of those 2.4Ghz transceivers. The maximum output power will be 20dBm. I am confused about the antenna. I really like to use a microstrip antenna for cost reasons but am worried(lack of knowledge) about the performance. I looked for RF connectors, namely UFL...
You can use a bandgap reference to generate it.
I don't remember the name of the circuit but you can also use a a simple n-channel current mirror(1:N) with a resistor between the source and ground of N-size MOSFET. The load for both the transistors is a p-channel current-mirror load. I think...
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