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Hi,
I am facing S14 DRC voilation during ATPG. I gone through Synopsys Manual but didnt get much info. If anybody come across S14 DRC voilation. Please let me know. The S14 is "Excessive scan cell states due to cell_type instance_name (gate_id) in chain scan_chain".
Thanks
Kiran K S
98866...
Scan Chain Test Pattern
All
ATPG tool generates the chain test pattern in the form "001100", why is it so? what is signifcance? why cant generate the 0101010 or "000111000" or other pattern
Kiran KS
Tester clock.
In IP, there are two clocks one is at 240Mhz and other one 1.2GHZ. I generated the patterns and how to check the patterns in tester? becuase Tester should not support such high frequency. I know one solution is using these clock, run at slower frequency i.e shift frequency. Is...
First check the scan chain pattern is passing or not? if it pass, then check which pattern is failing. Before that check properly all u r library cellls proper ot not? it is very important. Do paarallel simulation, check which flop is failing, transcript will give clear picture where it is...
DRC Voilation
Hi
Regarding the DRC violation, during the scan insertion solved all drc violations like Scannability rules(S1, S2 in DFTAdvisor). Can we get C1 rule violation in ATPG(FastScan) during pattern generation? If Yes, please explain.
DFT Questions
1)Is it recommend to have tri-state bus in the design, if so what precaution needs to be taken during design
2)Functionally it is taken care that the existing tri-state bus drivers can never create bus contention. Is this sufficient for Scan shift and capture? Do we need to take...
Hi All
Anybody worked on both DFTMAX(Synopsys) and TestCompressor(Mentor Graphics)? What exactly difference between both? what are the merits and demerits of both tool? Please let me know
scaninsertion
I am doing first time scan insertion. What are the requirements for scan insetion from the design team or front end team, TEST point of view
fastscan nofault
While running Fastscan with the hier Netlist, few instances (UO_DFT\A as an example) are marked as nofault. As I understand the under the instance the whole of the combo logic and the sequential logic are considered as Black Box by the ATPG tool.
Now that the hier...
lockup latch ocv
There are two clocks in a design, when we are doing scan insertion, adding lockup latches for avoiding the Clock Skews. Is there any other method to avoid clock skew in multiple design other than lockup latch? please let me let know
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