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Hi,
Some one please help to perform power analysis and estimation using EPS, I have VCD file and gate level netlist as my inpputs.
Please help me, I need flow to perform.
Thanks,
Kirangu
Hi Kuxx,
Thanks, it was helpful. I have a question here, during bottom up uproch, when our design is @ initial stage, lets say we have a dummy netlist or a black block netlist, how do we approach to get a budgeted .lib.
Thanks,
Kiran
Hi,
I am writing out lef from SoC encounter and by default too is placing all layer obstruction all over the block.
When I read same lef in top level blockage is visible all over the block.
How do I control it till the particular layer and particular portion.
For ex: If I have block of 500 x...
Hi All,
How can I get combo logic levels count ,
- from every input port to the first flop
- flop driving the output port to the output port
Please help me in finding it out in Olympus/ ICC.
Thanks,
kirangu
Hi,
I am planning to write a timing debugger script, which should dump out a report which briefs out reasons for the failure of top 10 failing end points.
Reason1 : Can be higher Skew
Reason2 : cells which are low drive cells.
Reason3 : Xtalk
Reason4 : bad tran/cap due to Fanout
Reason5 ...
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