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From datasheet, but it is not so clear.
can someone explain?
The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined
in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the
POR signal...
Doe's it make sense this is the reason that signal not absolutely zero?
During FPGA wakeup time Input is not defined so PMOS and NMOS a bit conducting due to the weak pullups with HIGH resisting.
The external pull down resistor create the route I draw with the blue arrow and voltage divided...
Red line - 3.3v FPGA VCC
Blue - FPGA internal Clock
Yellow - output signal from FPGA.
The question is why before the clock start, I see middle value for the output signal.
The signal have external pull down resistor
Hi,
When my fpga got 3.3v it take 28mS untill fpga wake up and the internal clock start working.
During this 28mS my output gpio get unvalid value of 0.9v even though the IO pulled down as can see in the picture. Any idea why during wake up the IO is not absolute LOW?
GPIO is defined push pull...
If I change the MASK value from (FFFFFFFF) to something else the programming is successfully finished but The FPGA don't functionality as expected.
1652711182
This is not a private project and I must use the lattice programmer, the FPGA (chip) assembled on PCB and not evaluation board
Someone know what the meaning of this line in the SVF file?
SDR 32 TDI(00000000) TDO(00019020) SMASK(FFFFFFFF) MASK(FFFFFFFF)
I tried to program "GOWIN" FPGA with lattice JTAG programmer and I don't succeed.
As I know, the JTAG programmer should be generic.
The programmer is successfully scan...
Hello,
I have an input signal that can be initiate at "0" or "1".
I want to detect if the signal changed from "0" to "1" or from "1" to "0" @ posedge clock
How can I do it?
I tried:
Always @ (posedge clk) begin
if (~input_signal)
xxx = 1'b0;
end
Hi,
Always when I tried to calculate and save big numbers I got an error:
ERROR - Design doesn't fit into device specified, refer to the Map report for more details.
and this is the Map report:
that is happen just after I add this lines to my design:
reg [15:0] rpm_counter;
parameter K =...
Hi
thanks for answer. I tried to do that but now when I try to map my project I got an error:
ERROR - Design doesn't fit into device specified, refer to the Map report for more details.
I guess because the big numbers arithmetic.
This is my code...
Hello,
I have a design that include counter.
after I finish to count I want to normalize the counter as below:
NUM = 15/(counter*0.000000221)
I want that NUM to be integer.
Example:
counter = 15000
NUM = 15/(15000*0.000000221) = 4524.886878 = 4524(rounded)
at the end I want to save to...
I also prefer UART.
So I understand from the hardware side all I need is usb to uart bridge.
With the implementation on FPGA side I will be OK.
But my problem is the implementation on PC side.
Are there any generic software I can read and write data?
In the future I want to build my own GUI...
How do I drive the signals from the computer using the usb?
How do I write the GUI? I want a standalone software.
I am not surw hiw to start.
At the beggining I want to drive the uart/spi signals from my pc.
Hello,
I will explain what I want to do step by step and maybe someone will be able to guide me how to get started.
First of all I will tell that I have knowledge in: analog design, digital HW design, FPGA, verilog, Arduino, C, Python and more.
My goal: I want to communicate with my FPGA device...
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