Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You should write the HDL code this
initial
$readmemb("blk_mem_ram.mif", mem, 8'h00, 8'hff);
always @ (posedge clk) begin
if (mem_rd_en) begin
mem_data_out <= mem[mem_addr_out];
end
if (mem_wr_en) begin
mem[mem_addr_in] <= mem_data_in;
end
end
and ISE will know that what...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.