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Hello all
Here are two vhdl codes (code-1 and code-2) both are separately work correctly, I wish to merge both codes please help for this.
code-1
--4 BIT BINARY COUNTER
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic...
Respected Fellow i have write following code, it is synthesis successfully, but there is some missing in code for my requirement which is;
Frame length = 1600 bits
Frame Header = ac52 (transmit msb first)
ac52 -----------(1584 bits"0")--------------ac52 -----------(1584...
Thank you for response, "ac52" is header of frame, I want to transmit "msb" first. Now I am able to define my frame:
Frame length = 1600 bits
Frame Header = ac52 (transmit msb first)
ac52 -----------(1584 bits"0")--------------ac52 -----------(1584 bits"0")--------------ac52
Dear Friends, I have just start the using CPLD, I need a vhdl code for a 16 bit shift register, who serially out a 16 bit pre-defined hex code like"AC52" on each rising edge of input clock. thanks
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