merge two or more vhdl code

[Khurram1965]

Hello all
Here are two vhdl codes (code-1 and code-2) both are separately work correctly, I wish to merge both codes please help for this.

code-1

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Code VHDL - [expand]
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--4 BIT BINARY COUNTER
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity counter is 
port(  clk:  in std_logic;
  reset:  in std_logic;
  enable:  in std_logic;
  count:  out std_logic_vector(3 downto 0)
);
end counter;
 
architecture behav of counter is         
  signal pre_count: std_logic_vector(3 downto 0);
  begin
    process(clk, enable, reset)
    begin
      if reset = '1' then
        pre_count <= "0000";
      elsif (clk='1' and clk'event) then
        if enable = '1' then
          pre_count <= pre_count + "1";
        end if;
      end if;
    end process;  
    count <= pre_count;
end behav;

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code-2
bcd to 7 segment driver

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity test is
port (
      clk : in std_logic;
        bcd : in std_logic_vector(3 downto 0);  --BCD input
        segment7 : out std_logic_vector(6 downto 0)  -- 7 bit decoded output.
    );
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
 
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case  bcd is
when "0000"=> segment7 <="0000001";  -- '0'
when "0001"=> segment7 <="1001111";  -- '1'
when "0010"=> segment7 <="0010010";  -- '2'
when "0011"=> segment7 <="0000110";  -- '3'
when "0100"=> segment7 <="1001100";  -- '4' 
when "0101"=> segment7 <="0100100";  -- '5'
when "0110"=> segment7 <="0100000";  -- '6'
when "0111"=> segment7 <="0001111";  -- '7'
when "1000"=> segment7 <="0000000";  -- '8'
when "1001"=> segment7 <="0000100";  -- '9'
 --nothing is displayed when a number more than 9 is given as input. 
when others=> segment7 <="1111111"; 
end case;
end if;
 
end process;
 
end Behavioral;

---

 

[kingslayer]

Dear Khurram1965,

I guess you're trying to let the counter do the count, and then let the 'test' module prepare bitmask for a 7-segments LED, isn't it?
In that case, all you need is to create a third VHDL design file called 'top', in which you instantiate the two designs you provide as 'components'; then you have to connect input/output ports appropriately. This is usual bottom-up approach for designing a circuit.

Best regards