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A question of a novice
The logic of one FPGA is divided into two parts which are designed by two men respectively. They use different synthesis tools. One uses xilinx XST and the other uses Synplify. When the two parts of code are combined into one design, neither synthesis tools can assure...
Thank u very much!
By often I mean sometimes the datas read back are right, but in most cases are wrong.
We've used scope to capture the waveforms of the signals and they accord with the timing specification quite well.
We've tried several address patterns and the problem still exits.
We've developed a DDR memory controller in Xilinx FPGA. The waveform of the control signals from FPGA to DDR memory seem to accord with the specification well, but the datas read from the memory ofen do not equal to the ones been written to it.
Did anybody has any experiences about such...
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