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Hi
You would undertake a diffusion step with oxygen (dry) as the wet oxide would grow far too quickly to achieve such a thin gate oxide.
You as the designer will choose the temperature. In actual processing 1000C is usually taken to create a high quality gate oxide, but as the temperature...
Hi Kimaya
I dont have the code to hand but there are excellent examples in the Silvaco examples section. There is an explicit example on how to alter the code so you can have a variable gate length which you can change the variable accordingly to scale your gate length. Since its in the...
There are a number of solutions;
You can extract a CV curve using ATLAS and sweeping the voltage and defining the steps. You could then consider plotting 1/C^2 vs voltage to extract the threshold voltage.
Alternatively both ATLAS and ATHENA allow you to extract the VT voltage directly, which...
Your active load vd sat will probably be around 0.3 v for the diode connected transistor you could redesign the diff input but i think better to do pass transistor.
Substitute 100mv into vgs minus vt then rearrange to find a new width. As vds sat decreases width mst incrase for a set constant...
Have you considered designing the pass transistor with a Vds sat of 150mV? and then setting W & L for 50mA?
Subthreshold is when the overvoltage Vov is between 70mV to 100mV, so for strong inversion you will need ~ 150mV vov which is the same as Vds sat. Does this help?
Hi
Ar you aware that you can use pwer resistors and heat sinks? Perhaps you could consider using one as a degenarite source resistor.
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Hi
Ar you aware that you can use power resistors and heat sinks? Perhaps you could consider using one as a degenarite source resistor.
Hi
I am not clear on what you are trying to achieve - are you able to send me a schematic of how you intend to set up the op amp and the bipolar transistor with any loads attached including your power rails? If you are using a discrete bipolar device you should have access to all 3 output pins...
Hi Junus,
My Skype address was given in my previous post, again it is Kenneth.Potter4
Can you let me know what you would like to discuss as my post was to answer questions regarding Anand's problem.
Regards, Ken.
Hello everyone,
If I may propose the following. If we assume that both the NMOS and PMOS transistors are held in saturation and that the output voltage is 0.5*Vdd if we let Vgs-Vt = 0.2 then gm=10*Ids.
Maximum gain is Av=gm*(Rp||Rn)=5Vdd
This implies gain increases with supply voltage.
Any...
Hi Adi,
Have you considered mismatch between the two transistors? It is highly unlikely that the two Vce of the transistors will also be equal. The Early voltage also plays a role, yes.
Regards Ken.
Dear Mariz,
It would be best to approach a supervisor who has project proposals or if you have an idea in mind to identify a supervisor in your department with a background in this area. You want to ensure that your supervisor is able to provide technical guidance and ensure your proposal is...
Hi Kingearlkwan,
I have attached a simple schematic of a voltage controlled current source. The analysis is straight forward. We have an op-amp configured as a follower and the negative op amp terminal attached to the source of the transistor. Since the op amp will have a very high open loop...
Hello Matinking,
Well there are a number of issues that I can see before evening begining to consider any basic calculations. If memory serves an IRF530 will have a threshold voltage or around 5V so your 5V nand inverters are going to hardly even be able to drive your devices into an on state...
Hi Imperza,
Attached is a pdf which discusses various techniques for extracting threshold voltage as dick has mentioned each of these techniques will provide a slightly different value for threshold. The key is to use one and keep with it for measuring all your devices. I have used the second...
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