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Hi,
Can anyone please explain in detail how the limit is set for clock tran and data tran?
I know it is based on some percentage (% ) of clock_period.
Like :
clock_tran limit --> x% of clock period
data_tran limit --> y% of clock period
But, I just want to know how they come up with that...
Hi Paul,
Thanks for the explanation.
I have a small doubt here.
Does generated clock remains in the same phase as main clock?
As I know main clock and generated clocks are synchronous to each other.
Thanks,
Karthik
Hi,
1. How do we confirm if the two clocks are synchronous/asynchronous to each other. ( on the basis of frequency ,phase and clock generator )
2. Can we confirm that Main clock and the generated clock which is generated by main clock are synchronous to each other ?
If yes/no m…why?
Can...
Hi,
I want to know the placement of a port in by block(which side it is sitting).
Is it possible to find the side of a port through command?
If possible, please give me the command to find that
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