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read_vcd -vcd_module top_inst -module m1_classifier_chip -activity_profile -start_time 0 -end_time 100000 -time_window 10000 -simvision /MicroE/microe01/units/AUDIO/HVT/compute.vcd
I've run my script in Cadence Encounter RTL compiler. Above is part of the code that is in the .tcl file. Whn i...
Thank you! I get a better understanding now. :)
Do you happen to knw what is 'leakage', 'internal' & 'switching' power is for a transistor? in a simple explanation.
for read_sdc. it says 'RTL compiler creates a cost group for each clock defined in the file.' What does cost group mean?
---------- Post added at 11:39 ---------- Previous post was at 11:21 ----------
for read_sdc. it says 'RTL compiler creates a cost group for each clock defined in the...
Hi everyone. I need to understand these following 3 lines from my .tcl file. Can someone please explain the bold codes to me? Thanks in advance!
read_netlist /MicroE/microe01/units/AUDIO/HVT/final_hvt.v -top ml_classifier_chip
read_sdc /MicroE/microe01/units/AUDIO/HVT/final_hvt.sdc
read_vcd...
if logic '1'is being applied, a logic '0' is what comes out and vice versa. power is not consumed when both of this conditions are applied. i would like to knw what is the condition required for power to consume.
Hi everyone. there is usually no power consumed in an inverter. Bt im required to find out a condition that allows an inverter to consume power. does anyone of u knw the condition? Thanks in advance!
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