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Recent content by kannanunni

  1. K

    Constraints in a design

    Try this : define_clock -period 100000 -name clkin [get_clocks CLK]
  2. K

    Calculating spacing between metal5 stripes

    Ok. i shown M5 here for simplicity, i don't use M5 for mesh. my mesh consist of M12(H),M11(V) top ring and M11(V) stripes, its connected to M6(H) and its again to M3(V) and then M2 for site row rail. upto M6 i can able to create stripes with out any warning. but while creating M3 stripes i get...
  3. K

    Calculating spacing between metal5 stripes

    how to calculate M5 spacing while adding power mesh. lef only having spacing table not the minimum spacing value. for higher metal layers its having minspacing value, lower layer spacing table only there. so how to calculate spacing fro this table and what is PARALLELRUNLENGTH in that. LAYER...
  4. K

    Getting Started with Encounter and TSMC 65 nm DK

    you need to map the in/out port with IO cells and after that route the connection with the IO pin.
  5. K

    Worst path categorisation in RTL compiler

    ok. that's solved. how to create path_group in rc compiler? i want to create r2r path using path_group command and find. so how to detect all reg output and input using find command? can i make it in a single command? or should i write tcl script with reg expressions for finding reg ports...
  6. K

    Getting Started with Encounter and TSMC 65 nm DK

    do you have any .io file from fab/design ? this file help to solve the issue. or you can edit pin and connectivity information from encounter itself.( edit -> pin editor)
  7. K

    Static Timing Analysis in the presence of Process Variation

    you need to add OCV libraries for that. cadence ETS can also be used for this purpose.
  8. K

    Clock Uncertancy vs Clock Freq increase

    that's right. frequency change wont affect hold but it affect setup.
  9. K

    STA & Async paths

    STA tools will report async path violations(recovery and removal) and we can specify delay in async path with the command in ETS set_max_delay (with respect to clock edge).
  10. K

    Why there is separate library for OCV

    why fab provides separate .lib for OCV even-though it has .lib for corner analysis? ie, only derating factors(early and late) for clock path timing and data path timing is only specified in this .lib right? so why don't they try to mix it with .lib for corner analysis(resulting in a .lib with...
  11. K

    Why do we need to run typical corner for signoff?

    i think typical corner check is not preferred in timing sign Off because the design has to work in TT if it passes fast and slow corner.
  12. K

    Clock Uncertancy vs Clock Freq increase

    In ideal mode the clock signal can arrive at all clock pins simultaneously. But in fact, that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty. Major reasons for the...
  13. K

    Fixing recovery and removal violations in postCTS stage

    At what point we are able to fully fix both these recovery and removal violations? Can do it at postCTS itself or postRoute and please provide some guidelines for that.. which is the effective way to resolve this violations either adding buffers in asyncpath or resizing clockcells(in the case...
  14. K

    [SOLVED] Why do we fix set up violations in pre CTS stage and hold violations after post CTS?

    OK. that's a good briefing about setup and hold, Thanks Sharath.
  15. K

    Tristate inverter buffer not found

    my initial tool configuration file is like this.. set_attr source_verbose 1 / #proc log_source_command { command filename line_number } { puts "<CMD> $command" } # ===================================================================== # * Define the Library #...
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