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Recent content by kangalooj

  1. K

    JESD204B with two different device clocks

    Is there any chance to make JESD204B works with FPGA hava different device clock than ADC but share same sysref and sync clocks?
  2. K

    Designing SDR Platform

    I have designed SDR (Software Defined Radio) that works with PC (and only PC with Windows because my SDR written in C#!). My SDR produce signal samples (16bit I/Q with 8MSPS rate) that I need generate them in real world ! So I need an interface between PC and second HW that generates signal to...
  3. K

    Designing SDR Platform

    My SDR must feed the signal generator! I want to generate samples in my SDR and transfer it to DAC via PCI-Express.
  4. K

    Designing SDR Platform

    I need to generate a signal have 16-bits samples (I and Q each 16bits) with 8 MSps sample rate, to use with my SDR (Software Defined Radio). I want to generate signals on the fly, so I can't store signal on disk and I must have near real-time communication with the hardware (a buffer of 100 to...

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