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Recent content by kandaka

  1. K

    multiple assign statements to a signal signal

    hi, in one of the designs i have seen the code sth like this assign BP = CK; assign BP = PT0; assign BP = PT1; will it not create any multiple driver issue ? if we drive CK,PT0 to 'Z' then what will happen ? what wil be resulted from this code in synthesis. Thanks , Prashanthi K
  2. K

    events in System Verilog

    is event in SV is bidirectional ? if we have 2 events ack and done -> ack event done =ack; ->done; always @ (ack) begin $display("ack event emitted"); end always @ (done) begin $display("done event emitted"); end if we trigger the event done will it trigger ack also ...
  3. K

    project in System Verilog

    system verilog project actually i am new to SV and VMM.So planing to develop the environment for any protocal or DUT so that i can use the main features of SV. Please suggest me regarding this
  4. K

    project in System Verilog

    verilog projects Hi, I am planing to develop System Verilog environment for any application from stratch.So,Can anyone suggest me something regarding this. Thanks in advance.
  5. K

    Error in SystemC compilation

    error in systemc hi, I am new to SystemC. We are trying Cadence Incisive Unified simulator to run SystemC programs. but we are getting this error Could not load SystemC model library libncsc_model (./libncsc_model.so: undefined symbol: _ZN8stimulus4testEv). ncsc_run: *E,TBELABF: ncelab...
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