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Hi everyone,
i got pop up for every time while booting my system,windows script host pop not able to disable. How to fix this issue.
https://imgur.com/a/yD7QU1U
i opened this file in .vbs format.
Set WshShell = CreateObject("WScript.Shell")
WshShell.Run chr(34) &...
Cadence software 16.6 hanged due to updating any thing in board file ?
Hi everyone,
i am using cadence allegro 16.6. i am doing one board which is 2 layer board only. i am facing some issue if add shape in my design (software is hanged, it is not reponse). i waited more then one hour to...
Hi everyone,
what is the different between cross talk and parallelism ??
cross talk means two signals are running in parallel so one trace coupled with other trace so, cross talk occur right like that parallelism means what ??
Hi everyone,
i worked in DDR2 and DDR3 Routing but. i studied some document related to DDR. For DDR3 Fly by (Daise chain) Topology is the best.but in DDR2 Address groups are routed in T-topology.
Here i attached DDR2 image. T-topolgy used.why we should not route the address signal group in...
Hi Everyone,
i am currently working for Dx-designer to PADS Layout flow.In General, if i want to find the UX ? in schematic which will highlight or show that footprint in Layout.That cross reference or cross probing i could see in Cadence allegro tool to sync up the orcad and PCB Editor tool...
Hi everyone,
i need to create this Die package.N-channel Power MOSFET has Source ,Gate and Drain pad need to create but in this datasheet ,i have pad size for Gate (widht not mention for Gate) and Source,but Drain mention as Back side.so How to create this Die package.
Package information...
Hi,
1.For PAD size use 1mmx0.2mm
2.solder resist should be 0.1524 mm (6 mils)
3.i could not understand your third point
4.yes,you should create center PAD
minimum solder resist to solder resist 3mil need to maintain
Hi,
File-->export--->library--->Pop up window open select no library depend box and select the library path
you will get .psm,.dra file in your assigned path
Hi,
Thanks for your valuable comments. Let me explain any one should I route the clock signal in between data Group (byte).if I route between the group will it be a signal integrity issue.(cross talk, radiation) ??
Hi everyone,
In my Board DDR3 section has some issue,Let me anyone give the solution.
DDR clock (Clk_0 & CLK#_0).Routed in top layer(Microstrip) because due to the less number of layer count.(Board has Eight layers)Four 4 DDR section used so, 64 Data signal occupied in two inner layer and...
Hi,
better try the orcad 16.6 for windows 8 and 16.3 will work on perfectly,check this blog
https://community.cadence.com/cadence_technology_forums/f/27/t/17097
Hi
Thanks for Both.Right now Density of board will be reduce once SOC come to the PCB Right ??that time no need for More PCB designer Right ??.Nowaday people working for Density of High speed but SOC will be reduce work for PCB designer ??
Hi dude,
Please explain about how will be PCB design field.Because right now System on Chip came to the Market which will affect the PCB design Field right ??
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