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Re: TEST BENCH
Rather than the number of lines, what is more important is the complexity of your design. More the complexity, more the test cases you need. Testing all the possilbe condtions using Modelsim can be very cumbersome. If you write a test bench or multiple test benches to test the...
Re: Timing Constraints
Though you have given a constraint of 100 MHz, your design is probably not able to work at more than 54 MHz.
I am not sure about the settings in ISE to do timing optimization.
If you want the currently implemented design to work reliably on the FPGA, you will have to use...
The integer to bit converter in the communications blockset should serve your purpose.
www.mathworks.com/access/helpdesk/help/toolbox/commblks/ref/integertobitconverter.html
Re: Verilog coding query
Try replacing the > in each of position finding statement with >=. For example
//Maximum position
assign pos0 = (corrouti1 > corrouti2) ? 5'd1 : 5'd2;
with
assign pos0 = (corrouti1 >= corrouti2) ? 5'd1 : 5'd2;
As mstrcosmos has rightly pointed out, it is not possible...
Re: Verilog coding query
This is probably one possible way of doing it. I have not compiled it, hope it does not have syntax errors and hope it works fine.
module sambig(clock,reset,Enable, corrouti1,corrouti2,corrouti3,corrouti4,corrouti5,max_value,max_pos) ;
input clock;
input reset...
Multiple Vdds are used in different parts of chip..not between FFs ..
Multi Vth cells can be used in any part of the design to save leakge power.. but Multi Vt process may be slightly costlier..
Hi,
Based on throughput requirements frequncy is decided. If your design has positive slack, you may delete some pipeline registers to save hardware..
rgds
k_vlsi
vlsi beginner
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