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these are "inherited connections" driven by the pins at the levels above, so you won't get pins in the digital cell. From a layout point of view either use a tie cell that connects to the pwr/gnd or manually add p/n diff ties.
it's not that the charge is negative or positive, the charge will aways want to go to ground. The device choice is if you are placing in an nwel or substrate.
The diode size is usually the default size, as small as possible.
Antenna errors can also be resolved without using diodes, the...
For the node that has the lower metal, take it up the the highest metal and back down so both ends of the mim cap start from Met5 ..
A node: Metal 5 > Signal
B node Metal 4 >Via4> Metal 5 > Via4 >Metal 4 > signal
This will balance the mim cap.
This is the Way...
That looks like multiple floating sub or nwell well exists, check for open substrate/nwell connections, connecting thru diffusions only or not at all.
Search for ERC/ ERC errors in the forum.
the resistance would be reduced, capacitance increased but your not looking at large amounts. Better for DRM (design for manufacturing) I doubt it would affect timing but might make routing more congested.
poly branches could indicate the numer of fingers in a device( never heard it described as such) , eg, width =1x 10um or 2x 5um. No of groups not a common name for multiplier.
Grouping is normmally associated with grouping common transitors or groups of resistors or both etc.
Hey, I'm looking for some pointers please.
I have
File A: is an extraction file, example /projectname/verificion/cellname.LCKT
File B i: is a cadence file, example /projectname/cadenceLibs/cellname.oa
Both files have varibles such as location and cellname.
I'd like to a script that can...
I design power products (layout) as mentioned the foundry design rules will provide max current density, take into account tempreture changes and balanced roututing, you may also want to concider using combs.
We use a tool called magwel to simulate the layout, it's quite good but needs CAD...
Design For Manufacruing rules are set by the process fab and they recommend using them to improve the yeild and relibilbilty of a chip.
The rules would recommend usage of straight and 45 degree angles, double via usage and metal paths than minimum, eg 0.18um path coule be 0.2um (>10% increase)...
I want to create a symbolic link using a script.
Within cadence I've saved the wire assistant settings to which I wish to share to the rest of the team.
I have saved the file in the general folder to which everyone has access , is there a way to run a script that will automatically create a...
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