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Recent content by juliewxh

  1. J

    How to deal with/avoid the noises on the clock signal caused by the voltage ripple in the power supply?

    Thank you so much for the suggestion and the documents. I'll study them and discuss them with our analog engineer.
  2. J

    How to deal with/avoid the noises on the clock signal caused by the voltage ripple in the power supply?

    @Easy peasy We put the clock signal from the clock generator to the clock pin inside the chip by sticking a probe to that pin, then measured the wave on the connecting wire. @D.A.(Tony)Stewart Thanks for the suggestions, I will forward them to our analog engineer to see if we can do...
  3. J

    How to deal with/avoid the noises on the clock signal caused by the voltage ripple in the power supply?

    Thanks all for replying, I really appreciate everyone's help(y). We do have a decoupling capacitor on the power rail and here's the result of the simulation when applying the instantaneous power: It seems not like the issue of the power rail then. We suspect the noises on the clock signal are...
  4. J

    How to deal with/avoid the noises on the clock signal caused by the voltage ripple in the power supply?

    Hello everyone, I encountered an issue that the clock signal got some noises on its edges during the transition (as is shown in the picture). It seems it's because the power supply has some ripples caused by the digital circuit's instantaneous power. The noises are big enough to make the...

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