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Recent content by juanMco

  1. J

    Low cost SOCs recommendation for a new project?

    Hi, Thank you for all the info. I have a question, does this chip have interfaces to connect DDR memories? I don't see connections to RAM memories in the development kits. For my design I will need at least 256 MB of memory to perform the processing of the analog signals taken.
  2. J

    Low cost SOCs recommendation for a new project?

    Hi, Very interesting and cheap option. I'm looking for the Github files but can't find them from Aliexpress page or googling the manufacturer. Can you tell me where I can get them? Thanks a lot.
  3. J

    Low cost SOCs recommendation for a new project?

    Hello all, First, I'm not sure if this is the right subforum for my question, if it isn't, I can create it in another one. I need to make an electronics that performs the following functionality: - Taking captures of analog signals from 2 channels, previously digitized using a 14-24 bit ADC...
  4. J

    MachXO2 and SFP transceiver data issues

    Hello all! I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs connected to a SFP modules and using single mode fiber cable. I'm using Lattice's MACHXO2 LCMXO2-1200HC-6TG144C model. The DDR interfaces work with clocks of 125 MHz, for...
  5. J

    MachXO2 DDR and PCLK routing issue

    Hi, First of all, thanks for the help. I had read the document but I did not understand it well, thanks for the clarification. Now another question arises: What I want to do is that when receiving a data through the receiving DDR interface (one bit in a clock cycle), the FPGA has to generate a...
  6. J

    MachXO2 DDR and PCLK routing issue

    Hello all! I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the received data. For the project I am using the MachXO2 family of Lattice. In...
  7. J

    Questions about migration from multimode to single mode fiber

    Hello all! In my company we are using custom measurement systems with multimode fiber optic transmitters and receivers for synchronization between different devices. We are thinking of migrating our multimode fiber optic technology to single mode to extend the reach to 20 km. The problem is...
  8. J

    Easiest way to generate fixed PWM signal

    Hello, I think I will choose the µC solution. I am looking for AVR ATTiny series and PIC10F series. Assuming that I use a external crystal with 8MHz, F_CPU = FOSC/4 = 2 MHz, If I am not wrong, maximum resolution for the ticks on Timer will be 500 nS, so this is the "potential error" whitout...
  9. J

    Easiest way to generate fixed PWM signal

    Hello all! I need to generate a fixed high precision PWM signal, period T = 10 ms, time high TH around 300 us and amplitude 5 V. I was doing it with a 555 timer with low tolerance components but the best signal I can generate has around +-0.02 ms error on period. I need to do exactly 10 ms...
  10. J

    Peak voltage on switching NMOS.

    Hello, Yeah I understood the charge injection and I am already testing CMOS switch topology. I have better results but still mV range peaks on the output. With Vin =2 V is a low one and can work but in the final circuit I will have also Vin=10mV. I will try now to find a MOSFET with very low...
  11. J

    Peak voltage on switching NMOS.

    Hello everyone! I am having some trouble with a charging/discharging capacitor circuit. Here I attach the basic circuit: The "control" signal is a square wave from a 555 timer with period T=10 ms and TH= 250 uS to set up the switching for the transistor. "Vin" is the charge voltage for the...
  12. J

    Voltage divider for charge/discharge capacitor

    Hello Barry, Sorry if I explained bad.. The original circuit has a programmable switching power supply, so the "regulator stage" is not needed because the programmable power supply does the work. For that reason I am implementing a circuit with DPDT relays, attenuation stages and some digital...
  13. J

    Voltage divider for charge/discharge capacitor

    Hello all! I am doing a design to charge/discharge a capacitor to generate pulse output for calibration measuring. I started the design based on a previous circuit done by another coworker. The stage is show below: The circuit works properly doing the discharge when the square signal...

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