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Hi, everybody!
Does anyone have tips for floorplanning memories?
I have a circuit with 16 blocks of memory IP, and I'm doing the floorplanning of this type of circuits for the first time. I know that the pins of the block are in one side.
I don't know what is best place to put the memories.
I...
Hi, you can check this project: https://www.netfpga.org/
It's an open plattform to implement network devices. They use verilog but you could easily translate it to vhdl.
hi,
I'm trying to make a logic that activated a bit when a a register value change. I will use this with a register bank(32 of 32bits).
My first attempt was to copy the register to another register and at each clock compare the value of both, but this consume lots of area.
Another idea i...
Re: What is common use file format for I/O pads in ASIC flow
I would really appreciate to know this too!. I'm learning the Cadence design flow from RTL to GDSII and I'm trapped with this. I'm being looking the cadence manuals but i didn't find anything.
io cell i/o cell
Is there any similar command for cadence design flow? Some command in RTL compiler or SoC encounter to automatically instantiate pads.
I would like to know how is this report done. I'm been looking in the respective user guides but I haven't found anything. I'm guessing that maybe is one simple operation from the info of the technology library cells.
Thanks in advance,
Jorge T
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