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I know someone with a company that supports open source and even publishes app notes detailing exactly what you have to do to use it. A lot of his customers realized that it was cheaper to hire his company rather than develop the expertise inhouse.
A lot of the old stuff on opencores.org is...
There is a setup time requirement from the release of an async reset to the rising edge of clk in order to prevent metastability. This could be a glitch or it could be mean that the reset is released one cycle later.
This requirement only applies when you are trying to change state when you...
It's not never. You have asynchronously reset a flipflop to 0 and it has a 0 on its D input. You have a race between the reset
deassert trying to keep it at 0 and the rising edge of clock trying to set it to 0.
The winner is going to be 0. There is no way that it will somehow flip to 1 in...
If the flipflop resets to 0 and you have a 0 coming in on the D input then you do not need to synchronize the trailing edge of reset. It will remain at 0 no matter where reset aligns with clock. Same is true with a 1. The vast majority of flops in an embedded system design come out of reset and...
You can design without a reset and certain blocks like clock dividers that must function during reset do exactly that. But it only works for small blocks otherwise the verification is impossible and you still need another reset for simulation and test.
John Eaton
Your silicon vendor will give you a fudge factor like 1.070458 and tell you to synthesis at a certain process corner with your nominal frequency times the fudge factor.
If you pass with 0 margin then it should work at all process corners,
Inverting the clock solves the hold time issue on the RTL --> gates signals by providing 1/2 cycle of hold time. You need to be careful that your logic is fast enough to still meet the setup time with that late of input signal.
You also have a problem on the gates -> RTL signals in that the...
The only issue with a 2 cycle path is what happens on the first clock. It's input will still be in transition so it could go metastable on the first clock before going to the correct value on the second. Since it is probably feeding another 2 cycle input cone then that flop will be totally...
you are getting latches because you are never using clk. Change your always statements to always@(posedge clk) and the blocking (=) to non-blocking (<=).
Also take the write_enable out of the read logic. You should read something on every clock.
John Eaton
Reset and Enable are related and despite what some people have said they are both required.
Reset is used to put the circuit into a known good start state. Some circuits like clock dividers have to run during the power on reset time and they must be designed to self start and run from any...
Did you read my first reply where I told you NOT to do that?
Do not touch your current code. Add an additional async reset to all flops and connect that to your simulation reset. You will need two separate reset systems. An async one that is never driven
except by your simulator and a...
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