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You are right, I needed to write a mux for input data. Thx for your advise! In other part of the project I'm using different addresses signal, so I needed too define another mux for addr too and one for write_enable signal...
info:xst:738 -
I'm workin with Verilog and using ISE Compiler. My problem is RAM inferrention for a signal. ISE is impementing my signal in FF and I don't know why. The code:
reg [31:0] ct_tab_start_next_n [7:0];
always@(posedgeCLK)
if (ag_start)...
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