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Hi
'm having ADC chip "ADS 8364" wit 25M Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process.
my problem is before writing vhdl Code i want generate timings ADC to FPGA but
(1) i don no what is this timing generation ?
(2) why this is...
Re: Please Help me
[b]Thanks lot for yur Inputs ..
ya it Should be 16660 ON and 16660 OFF
abd yur One more input
*******************
I would suggest write
elsif(MHZ_clock'event and MHZ_clock = '1') then
clk_count <= clk_count + '1';
-----------
-- your code
-------
It should work...
Please Help me
Hello to all
i have master Clock 40 Mhz and from master Clock want Generate 1.2 Khz Square wave pulses at output
my code is as below
(1) what is problm with my Code
(2) how Counter works and how to decide the Counter values like
these designs
(3) without Counter can we use...
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