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Recent content by JoseL

  1. J

    Fast Ethernet RJ45 on gigabit transceiver

    Hello, I'm currently designing a PCB which will be connected to another board which contains a gigabit Ethernet transceiver (Marvell Alaska 88E1512). The thing is that I don't need gigabit with 100/100 Ethernet would be more than enough, so in my board I want to route the signals to this RJ45...
  2. J

    creating new vhdl files with Lattice icecube2

    Hello first of all thanks for your answer, Regarding your argument I completely disagree, in my opinion, a company with a big budget doesn't mean they go to have a "nice IDE" and "nice" software solution for their products. i.e I can talk about Xilinx, I worked and I still working with ISE...
  3. J

    creating new vhdl files with Lattice icecube2

    Ok that's like I'm doing it but I wanted to know if there's any other way... and how the people is working with this fpgas.. Thanks for your anwer.
  4. J

    creating new vhdl files with Lattice icecube2

    Hello all, I'm trying to work out with lattice ICE40 fpgas and the IDE for them is ICECUBE2 (I don't undestand why Lattice Diamond doesn't have support for this fpga family). I think that this IDE is a bit clunky but I can deal with that, the problem is I'm not able to create a new VHDL file...
  5. J

    RS232 vhd controller

    Thank you very much for you help and soon reply, I will have a look to the link. Thanks again. Regards.
  6. J

    RS232 vhd controller

    hello everybody, I’m trying to understand how is working the rs232 controller, and I thing I have understood nearly everything, the only thing I can’t understand properly is how calculate the oversampling value to get the data, I mean the baud rate. I’m working with the digilent’s code...
  7. J

    Gerber problem in allegro 16.5

    I'm using ORCAD software, the problem is that I need to generate the file .GTL .GBL..etc instead only I have the files *.art for all layers.
  8. J

    Gerber problem in allegro 16.5

    Thank you for your response but how I do that? is there a option in allegro or I need other soft?
  9. J

    Gerber problem in allegro 16.5

    Hello!, I need to generate the next gerber files to send a manufacturer: Top layer: pcbname.GTL Bottom layer: pcbname.GBL Solder Stop Mask top: pcbname.GTS Solder Stop Mask Bottom pcbname.GBS Silk Top: pcbname.GTO Silk Bottom pcbname.GBO NC Drill...
  10. J

    Disconnect signals in Allegro PCB Designer

    Hello! How can I disconnect a pin from a signal in Allegro PCB designer without using Orcad Capture, I mean, just in the PCB designer? I'm using v16.5. Thanks in advance.
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