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Recent content by joijac

  1. J

    combinational circuit design:RTL to GDSII

    thankx all...for repliess i would like clear abt a basic combinational circuit like 7400,7432(gates),adders,multipliers,encoder.how can make .gds2 file for those designs without virtual clocks?? thankz in advance!!
  2. J

    What is the purpose of "Verilog-XL" tool in Cadenc

    Re: What is the purpose of "Verilog-XL" tool in Ca kk.thankx for reply can you mention the purpose of the following options in Verilog-XL 1. Incisive verification environment 2. Incisive P2C Methodology 3. Incisive Design Team simulator 4. Affirma simulation analysis environment thankx in...
  3. J

    "import the design" option in SOC Encounter

    i have loaded the design through GUI only, is there any command avail to load??.plz assist
  4. J

    How to bring up the graphical interface of Verilog-XL?

    Re: verilog-XL hi, what's LDV stands for
  5. J

    What is the purpose of "Verilog-XL" tool in Cadenc

    what the purpose of "Verilog-XL" tool from Cadence? the options available in Verilog-XL's are: 1. Incisive verification environment 2. Incisive P2C Methodology 3. Incisive Design Team simulator 4. Affirma simulation analysis environment is it the option only for .sv file and its compiling...
  6. J

    "import the design" option in SOC Encounter

    i wrote the HDL netlist file in the following format: write_hdl -mapped dff_b > /Cadence/RTL_COMPILER/dff_nll.v write_hdl -generic dff_b > /Cadence/RTL_COMPILER/dff_nll.v but while importing in SOC its displaying like "Failed to read netlist"
  7. J

    "import the design" option in SOC Encounter

    dear all, i couldn't able to import the design in SOC.getting error after giving OK such as **ERROR:(SOCVL - 902): Failed to read netlist..?RTL_COMPILER?dff_nll.v(the path) if anybody knows the solution. kindly assist thankx in advance
  8. J

    combinational circuit design:RTL to GDSII

    Dear all, How can i give constraints to a combinational design in SDC format. wt all the RC commands and basic constraints for a combination design? kindly help Thankx in advance
  9. J

    ioc file in SOC Encounter

    Dear all, How to make .ioc file for SOC. If anybody knows, kindly give the format or method to to write .ioc file. or Is there any option to generate .ioc file in SOC? kindly see.awaiting for the reply from techiess thanx in advance[/b]
  10. J

    import the design option in SOC Encounter

    dear all, i couldn't able to import the design in SOC.getting error after giving OK such as bad option "**ERROR:(SOCSYT-6729): bad option "**ERROR: technology file or a LEF FILE. ":must be blank, cget, configure, copy, data, get,put, read, redither, transparencey, or write...
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