Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

combinational circuit design:RTL to GDSII

Status
Not open for further replies.

joijac

Newbie level 5
Joined
May 29, 2010
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Activity points
1,345
Dear all,

How can i give constraints to a combinational design in SDC format. wt all the RC commands and basic constraints for a combination design?

kindly help
Thankx in advance
 

salma ali bakr

Advanced Member level 3
Joined
Jan 27, 2006
Messages
971
Helped
104
Reputation
206
Reaction score
21
Trophy points
1,298
Activity points
7,491
for constraining combinatorial logic, you don't need to associate input and output delays with a clock....it's the opposite of constraining sequential logic, where you always need to link your block with a clock
 

xchuang19

Newbie level 2
Joined
May 14, 2010
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
whether to create a virtural clock or not is determined by your system and interface requirement, u may think about the max delay and min delay .
 

joijac

Newbie level 5
Joined
May 29, 2010
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
bangalore
Activity points
1,345
thankx all...for repliess


i would like clear abt a basic combinational circuit like 7400,7432(gates),adders,multipliers,encoder.how can make .gds2 file for those designs without virtual clocks??

thankz in advance!!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top