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Recent content by joe_chuang

  1. J

    How to translate Verilog (GATE Level) to Spice(with Standard Cell)?

    edif to spice To Jaz: I only have SPICE CELL, I don't have Standard Cell Library for Cadence. I have ever used Verilog In of Cadence to generate netlist. The Cadence will create symbol for Standard cell.But the pin order of the symbol doesn't match to Spice Cell. Would you tell me how to chang...
  2. J

    How to translate Verilog (GATE Level) to Spice(with Standard Cell)?

    Does any one know how to translate Verilog (GATE Level) to Spice(with Standard Cell)? Thanks.
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