Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear all :
I want to do the behavior simulation of DLL
(delay lock loop) by simulink. But I don't know how to get start.
Could you give me so tutorial of how to use simulink to simulate DLL
And, is there any example of DLL simulink ?
Thanks
Thanks for your explanation.
But I still can't figure out.
Could you give the original DFF before it is minimized and remove its D input ?
Thank you very much
dear all
the books said the phase detector is composed with two dff and an and gate.
but I wonder how to view this circuit as DFF
could you help me to understand it ?
Thanks
rc ladder
How to calculate the time constant of 5 order RC ladder ?
it's time constant is 5RC?
is it equivalent to the RC circuit with 5 times R and C value?
-R--R--R--R--R--- ---5RR-----
| | | | | = | ???
C C C C C...
Dear All
How can I use Hspcie to simulate phase margin v.s. load capacitance
Y axis is phase margin
X axis is load capacitance
I use .measure to get phase margin but I can't plot it on spice explore.
Could you give me some Hspice code to do this simulation?
Thank you
Added after 1 minutes...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.